1. Field of the Invention
The present invention relates to a photo-electric conversion device and an image capturing system.
2. Description of the Related Art
Japanese Patent Laid-Open No. 2002-152565 discloses a solid-state image capturing device in which a hold capacitance 26′ is connected to the gate of a load transistor 9 connected to an amplification transistor 4 of a photo-electric conversion cell via a vertical signal line 8 (FIG. 1 of Japanese Patent Laid-Open No. 2002-152565). A constant current source 25 is connected to the hold capacitance 26′ via switches 27 and 28. During a period the switches 27 and 28 are ON, the hold capacitance 26′ samples a bias current supplied from the constant current source 25. After that, during a period the switches 27 and 28 are OFF, the hold capacitance 26′ holds the bias current. According to Japanese Patent Laid-Open No. 2002-152565, it is supposed to be possible to suppress a fluctuation in the set current of the load transistor 9. Japanese Patent Laid-Open No. 2007-129473 describes a solid-state image capturing device in which a capacitor 7 is connected between ground and the gate electrode of a field effect transistor 10 which forms the load of a current source provided on a vertical signal line 2 (FIG. 1 of Japanese Patent Laid-Open No. 2007-129473). According to Japanese Patent Laid-Open No. 2007-129473, it is supposed to be possible to prevent a fluctuation in the potential of the vertical signal line corresponding to the current supplied from the field effect transistor 10 because a fluctuation in the potential of the gate electrode of the field effect transistor 10 can be suppressed.
However, Japanese Patent Laid-Open No. 2002-152565 includes no description about how to reduce the coupling capacitance between the vertical signal line 8 and the hold capacitance 26′. When the coupling capacitance between the vertical signal line 8 and the hold capacitance 26′ increases, the voltage held by the hold capacitance 26′ when a large signal is output to the vertical signal line 8 upon incidence of high-intensity light on the photo-electric conversion cell is readily fluctuated. Since this changes the gate voltage of the load transistor 9, the fluctuation in the set current of the load transistor 9 may be large. Japanese Patent Laid-Open No. 2007-129473 has no description about how to reduce the coupling capacitance between the vertical signal line 2 and the capacitor 7. When the coupling capacitance between the vertical signal line 2 and the capacitor 7 increases, the voltage held by the capacitor 7 when a large signal is output to the vertical signal line 2 upon incidence of high-intensity light on the pixel is readily fluctuated. Since this changes the gate voltage of the field effect transistor 10, the fluctuation in the constant current supplied by the field effect transistor 10 may be large.